In general, automatic test equipment (ATE) is equipment for testing electronic devices such as circuit boards or integrated circuits (ICs) in an automated manner. When an ATE system tests such a device (commonly referred to as the device under test or DUT), the ATE system typically applies stimuli such as electrical signals (e.g., voltages and/or currents) to the DUT and checks responses of the DUT. Typically, the end result of a test is either xe2x80x9cpassxe2x80x9d if the DUT successfully provides certain expected responses within pre-established tolerances, or xe2x80x9cfailxe2x80x9d if the DUT does not provide the expected responses within the pre-established tolerances. More sophisticated ATE systems are capable of evaluating a failed DUT to potentially determine one or more causes of a failure.
Some ATE systems can program and test bus-oriented components of a DUT. Programming DUT components customizes the DUT for its intended application. One such ATE system includes a controller, an input/output (I/O) interface, a tester and a bed of nails. Typically, the controller is a workstation or a personal computer (PC), and the tester is a channel card having multiple channels that enable the channel card to simultaneously provide and record multiple signals. The I/O interface typically connects the controller with the tester. Similarly, the bed of nails typically connects the tester with the DUT.
During operation, the controller sends numerous low level instructions and data to the tester through the I/O interface in order to configure the tester to program and test a specific bus-oriented component of the DUT. In particular, the controller provides signal generating data (e.g., signal sequences, voltage settings, voltage application time lengths, etc.), switch settings which control which portions of the bed of nails will be used during programming and testing, and test parameters such as those which define the length of the test and clock frequencies.
Once the controller has configured the tester through the I/O interface, the controller sends a special command to the tester, through the I/O interface, to begin programming and testing the specific bus-oriented DUT component. In response, channel circuitry within the tester generates signals having particular characteristics in accordance with the signal generating data. Furthermore, channel switches within the tester operate to route these signals to proper locations. As a result, the tester simulates one or more memory access cycles (e.g., FETCH, READ, WRITE, RESET, etc.) to program and test the bus-oriented DUT component.
Upon completion of the test, the tester provides recorded signal samples to the controller, through the I/O interface, for further processing (e.g., for a comparison with an expected response).
After the tester of the ATE system has completed testing of the bus-oriented component and has provided the results to the controller, the controller can reconfigure the tester to program and test another component of the DUT (e.g., another bus-oriented DUT component). To this end, the controller provides, through the I/O interface, new signal generating data, new switch settings and new test parameters which configure the tester to appropriately program and test the new DUT component. After testing of the new component is complete, the tester again sends the recorded signal samples to the controller, through the I/O interface, for further processing. The controller can repeat this process for other DUT components until the DUT is fully tested.
An ATE system which is similar to the above-described ATE system is described in U.S. Pat. No. 4,500,993 entitled xe2x80x9cIn-Circuit Tester for Testing Microprocessor Boards,xe2x80x9d (Jacobson), the entire teachings of which are hereby incorporated by reference in their entirety. Another similar ATE system is described in Reissued U.S. Pat. No. RE 31,828 entitled xe2x80x9cIn-Circuit Digital Tester,xe2x80x9d (Raymond et al.), the entire teachings of which are hereby incorporated by reference in their entirety.
In some conventional ATE systems a controller (i) configures a tester to program and test bus-oriented DUT components (as well as other DUT components), and (ii) receives recorded test results from the tester for further processing. In particular, for each component of the DUT to be tested, the controller typically provides numerous low level instructions and data such as signal generating data (e.g., voltage settings, voltage application time lengths, etc.), numerous switch settings, and test parameters to the tester through the I/O interface. Once the controller configures the tester using this information, the controller commands the tester to begin programming and testing that DUT component by sending a special command to the tester through the I/O interface. In response, the tester uses the instructions and data from the controller to properly generate signals and to properly operate the bed of nails which couples the tester to the DUT. At the end of each test, the tester typically returns recorded DUT component signal samples to the controller through the I/O interface for further processing.
Unfortunately, the data transfer rate between the controller and the tester, through the I/O interface, is often slower than the data transfer rate between the tester and the DUT, through the bed of nails. That is, more time is often required for the controller to configure the tester through the I/O interface, than for the tester to perform a programming and/or testing procedure on the DUT. Furthermore, upon completion of a test, additional time is required to transfer recorded test samples from the tester to the controller through the I/O interface for further processing. Such operation is essentially a bottleneck of the ATE system. That is, the numerous low level instructions and data passed between the controller and the tester for each DUT component test limits the overall throughput, i.e., programming and testing speed, of the ATE system.
In contrast to the above-described conventional ATE systems which require extensive use of the I/O interface to transfer numerous items of information (i.e., low level instructions, switch settings, sampled data, etc.) between the controller and the tester, the invention is directed to techniques for accessing an external device, e.g., programming and/or testing a DUT, using higher level memory access instructions between an ATE controller and an ATE interfacing apparatus, e.g., a specialized tester or channel card device. The use of such higher level instructions results in optimized communications between the ATE controller and ATE interfacing apparatus, and shorter overall programming and test times. Accordingly, the invention provides greater throughput over conventional ATE systems.
Furthermore, the use of higher level instructions enables ATE program and test developers to more easily develop ATE programming and testing procedures. For example, rather than require the developer to provide step-by-step details of the programming operation (i.e., numerous low level instructions), the developer can provide a few higher level instructions.
One arrangement of the invention is directed to an ATE system having a controller that provides a memory access instruction having a command and a test bus address; an interfacing apparatus (e.g., a specialized tester or channel card device) for accessing an external device (e.g., a DUT); and a test bus which connects the controller with the interfacing apparatus. The interfacing apparatus (i) receives the memory access instruction from the controller through the test bus, (ii) translates the test bus address into an identifier which identifies a portion of the external device, and (iii) accesses the identified portion of the external device based on the command and the identifier. Translation of the test bus address into the identifier, and accessing the external device based on the command of the instruction and the identifier alleviate the need for the ATE interfacing apparatus to receive numerous low level instructions and data. Accordingly, less time is needed to configure the interfacing apparatus through the test bus.
In another arrangement of the invention, an ATE interfacing apparatus has a test bus interface for connecting to a test bus of an ATE system (e.g., to a VXI bus); an external device interface for connecting to an external device; and a translator, interconnected between the test bus interface and the external device interface. The translator receives a memory access instruction from the test bus through the test bus interface. The memory access instruction includes a command and a test bus address. The translator translates the test bus address into an identifier which identifies a portion of the external device, and accesses the identified portion of the external device through the external device interface based on the command and the identifier.
In one arrangement, a memory address space of the ATE system includes a local memory address space for addressing memory locations of a local memory of the ATE system and an external device address space that is outside the local memory address space. Here, the translator is configured to determine whether the test bus address of the memory access instruction is within the external device address space prior to accessing the external device. If so, the translator translates the test bus address into an identifier and accesses the external device based on the identifier. If not, the translator does not access the external device based on the identifier. This arrangement enables ATE program and test procedure developers to use standard memory access instructions to access the external device as if the external device were part of local memory of the ATE system. Such tightly coupling is achieved by ability of the ATE interfacing apparatus to determine whether a particular memory access instruction is intended to access the external device (e.g., FLASH memory of a DUT) or part of the ATE system (e.g., local memory within an ATE controller).
In one arrangement, the external device interface is connectable to an external device bus of the external device (e.g., a PCI bus on a DUT). In this arrangement, the translator preferably includes an address sequencer that generates, as the identifier which identifies the portion of the external device, an external device bus address based on the test bus address. The external device bus address identifies (or addresses) a memory location of the external device. Accordingly, the ATE interfacing apparatus can access the external device using one or more external device instructions (e.g., READ, WRITE, etc.).
In one arrangement, the memory access instruction further includes data and the external device interface is connectable to an external device bus of the external device. In this arrangement, when the external device bus has a width that is different than that of the test bus, a data sequencer in the translator maps the data of the memory access instruction into a number of external device bus cycles that is different than a number of test bus cycles conveying the data to the automatic test equipment interfacing apparatus. Accordingly, if the test bus and the external device bus are different widths, the ATE interfacing apparatus can optimize data transfers by reformatting the data into an efficient number of bus cycles during data transfer.
In one arrangement, the memory access instruction further includes data and the translator selectively operates in one of a programming mode and a test mode. Here, the translator handles a WRITE command by writing the data into a memory location of the external device when the translator operates in the programming mode. However, the translator handles the WRITE command by reading data from a memory location of the external device and comparing the read data to the data of the memory access instruction when the translator operates in the test mode. This feature enables the ATE interfacing apparatus to program (e.g., write) or test (e.g., read and compare) in response to WRITE commands which generally require less bus bandwidth than READ instructions. Accordingly, programming and testing speeds are improved and throughput is enhanced.
In the above-described arrangement, the translator preferably includes an interrupt generator that generates an interrupt signal to a controller of the ATE system through the test interface when the read data from the memory location of the external device and the data of the memory access instruction are different. Accordingly, the ATE interfacing apparatus can notify the controller that data read from the external device does not match data or the memory access instruction, e.g., expected data, perhaps due to an error.
In one arrangement, the external device includes an external device bus, and the translator is configured to access the identified portion of the external device by (i) providing, on the external device bus, an external device instruction having an external device bus address as the identifier, and (ii) selectively providing at least one supplemental external device instruction to the external device on the external device bus based on the command of the memory access instruction. This feature is useful for programming particular types of devices which require more than one external device bus cycle for proper operation. For example, many older FLASH devices require an additional set of bus cycles called an xe2x80x9cunlock sequencexe2x80x9d prior to executing a write cycle to program an address. The translator of the ATE interfacing device is configured to selectively provide additional cycles (i.e., supplemental external device instructions) as necessary to accommodate such devices. This alleviates the need for an ATE controller to provide more than a single memory access instruction when programming a device.
In one arrangement, the memory access instruction includes exactly one test bus address and further includes a block of data which the translator, in response to the memory access instruction, (i) receives from the test bus over multiple test bus cycles, and (ii) provides to the external device. This enables the ATE interfacing apparatus to take advantage of a test bus with block transfer mode capabilities. That is, an ATE controller can provide a block of data to the ATE interfacing apparatus using a block transfer mode WRITE instruction, and the ATE interfacing apparatus will respond by properly receiving the block of data and writing it to the external device.
In one arrangement, the test bus interface, the translator and the external device bus interface operate in a pipeline manner to process multiple memory access instructions simultaneously. Accordingly, the ATE interfacing apparatus can handle multiple memory access instructions at the same time similar to many pipelined processing devices. Upon detection of an error, the ATE interfacing apparatus is configured to properly handle the error prior to xe2x80x9cbacking upxe2x80x9d and restarting the pipeline at a safe point.
In one arrangement, the ATE interfacing apparatus further includes a library of translation routines. The translator is configured to dynamically select among the translation routines of the library when processing multiple memory access instructions in order to access different portions of the external device in different manners. Accordingly, the ATE interfacing apparatus is equipped to program and test many different types of devices without the need to incrementally obtain numerous low level instructions and data from the ATE controller each time the ATE interfacing apparatus begins programming and testing of a different device.
Another arrangement is directed to a computer program product that includes a computer readable medium having code stored thereon for processing a memory access instruction. The code, when carried out by an interfacing device of an ATE system having a test bus coupled to the interfacing device, causes the interfacing device to perform the steps of: (a) receiving a memory access instruction having a command and a test bus address; (b) translating the test bus address into an identifier which identifies a portion of an external device; and (c) accessing the identified portion of the external device based on the command and the identifier. Such code can be bundled with an operating system of the ATE system for convenience, or provided separately.
The features of the invention, as described above, may be employed in an ATE system and other related devices such as those manufactured by Teradyne, Inc. of Boston, Mass.